![]() ![]() When using the Hold function the SPI transfer is paused. When configured to be the Reset signal, it simply resets the device when the signal goes low. Many manufacturers offer both options using either a different part number or a configurable register allowing the pin function to be changed by the host. Hold/Reset* This pin is either the Hold or Reset signal. The next figure shows a common pin assignment of an 8-pin device when using the standard SPI mode.įigure 1 – 8-pin QSPI pinout diagram in standard SPI mode. ![]() Regardless of which name is chosen by the datasheet they refer to the same thing, the well-known 4-wire SPI protocol. The standard SPI mode is known by many names by the various manufacturers: Standard SPI, legacy SPI, single SPI, single lane, single bit and finally extended SPI. As such, we’ll concentrate on the read command protocol while a deeper insight into the command set of QSPI NOR will be left to a future article. Consequentially the various read commands are more representative of the protocol variations than any other command class. Indeed, QSPI NOR Flash boasts one of the fastest random access performances of all discrete flash storage media, and excellent sequential read performance reaching close to 100 MiB/s sustained bandwidth. One thing to keep in mind is that QSPI NOR devices are optimized for read performance. We’ll start simple, with the basic SPI protocol then move through the variations to reach some of the more complicated QIO, QPI and DDR variations. Over the course of this article, we’ll go through most variations of the protocol used by QSPI NOR Flash devices. And as is usual with our articles, this series puts special emphasis on the impact of device features and characteristics on the software and application design. This series isn’t meant to be an introduction to NOR flash technology but is more about what differentiates one QSPI NOR flash device from another. ![]() In previous articles, we looked at the hardware characteristics of QSPI NOR devices and the internal memory organization of the flash memory. And to make things even more complicated, QSPI controllers often do not support all the variations.īut fear not, in this third entry on the ins and outs of QSPI NOR Flash devices, we look at the Quad Serial Peripheral Interface protocol and its variations in depth. As is the form for storage devices, not all variations are supported by every device family. Including the obligatory single, dual and quad data lane modes there are over a dozen variations of the base protocol. In practice, however, the answer isn’t as simple. Extend the common SPI protocol to use 4 data lanes, thus increasing the overall bandwidth. The concept of the Quad Serial Peripheral Interface, i.e. ![]()
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March 2023
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